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PC7410
PowerPC 7410 RISC Microprocessor
Datasheet
Features
* * * * * * * * * * * * * * * * *
22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated) 917MIPS at 500 MHz Selectable Bus Clock (14 CPU Bus Dividers Up To 9x) Seven Selectable Core-to-L2 Frequency Divisors Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V) Selectable L2 interface of 1.8V or 2.5V PD Typical 5.3W at 500 MHz, Full Operating Conditions Nap, Doze and Sleep Modes for Power Saving Superscalar (Four Instructions fetched per Clock Cycle) 4 GB Direct Addressing Range Virtual Memory: 4 hexabytes (252) 64-bit Data and 32-bit Address Bus Interface 32 KB Instruction and Data Cache Eight Independent Execution Units and Three Register Files Write-back and Write-through Operations fINT Max = 450 MHz 500 MHz fBUS Max = 133 MHz
Description
The PC7410 is the second microprocessor that uses the fourth (G4) full implementation of the PowerPC Reduced Instruction Set Computer (RISC) architecture. It is fully JTAG-compliant. The PC7410 maintains some of the characteristics of G3 microprocessors: * The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units * The microprocessor provides four software controllable power-saving modes and a thermal assist unit management * The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache
interface with on-chip L2 tags
In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency protocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec(R) technology instruction set. New features have been developed to make latency equal for double-precision and single-precision floating-point operations involving multiplication. Additionally, in memory subsystem (MSS) bandwidth, the PC7410 offers an optional, highbandwidth MPX bus interface. Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface.
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e2v semiconductors SAS 2007
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Screening
* CBGA Upscreenings Based on e2v Standards * Full Military Temperature Range (TJ = -55 C, +125 C),
Industrial Temperature Range (TJ = -40 C, +110 C)
* CI-CGA Package Version, HiTCE Package Version
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Figure 1-1.
1. Block Diagram
128 bits (4 instructions)
Instruction Unit Additional features Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor
2 Instructions
Instruction MMU
SRs (Shadow) 128-entry ITLB IBAT Array Tags 32-Kbyte iCache
Fetcher
Branch Processing Unit 64-entry BTIC/512-entry BHT LR/CTR
PC7410 Microprocessor Block Diagram
Instruction Queue 6-word
Data MMU Dispatch Unit
EA
SRs (Original)
PA
128-entry DTLB
DBAT Array
Tags
32-Kbyte DCache
64-bit (2 Instructions)
Reservation Station
Reservation Station
Reservation Station
VR File 6 Rename Buffers
Reservation Station
Reservation Station
GPR File 6 Rename Buffers
32-bit
Reservation Station 2-entry
FPR File 6 Rename Buffers
Reservation Station
Load/Store Unit
- Add EA Calculation Finished Stores Completed Stores
Vector Permute Unit
Vector ALU
VSIU VCIU VFPU
Integer Unit 1
Add-Multiplydivide
Integer Unit 2
- Add -
System Register Unit
64-bit
Floating 64-bit Point Unit Add-Multiplydivide FPSCR
VSCR
128-bit
32-bit 128-bit
32-bit
128 bits
Completion Unit 8-entry Reorder Buffer
L2 Controller L2 Data L2 Tags Transaction L2CR Queue L2PMCR
Bus Interface Unit L2 Miss Data Transaction Queue L2 Castout
Memory Subsystem Data Reload Data Reload Buffer Table
19-bit L2 Address Bus 64- or 32-bit L2 Data Bus 32-bit Address Bus 64-bit Data Bus
Instruction Reload Buffer Instruction Reload Table
PC7410
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PC7410
2. General Parameters
Table 2-1 provides a summary of the general parameters of the PC7410. Table 2-1.
Parameter Technology Die size Transistor count Logic design
Device Parameters
Description 0.18 m CMOS, six-layer metal 6.32 mm x 8.26 mm (52 mm2) 10.5 million Fully-static Surface-mount 360 Ceramic Ball Grid Array (CBGA) Surface mount 360 high coefficient of thermal expansion ceramic ball grid array (HiTCE) Surface mount 360-column Ci-CGA Package 1.8V 100 mV dc or 1.5V 50 mV dc (nominal; see Table 6-3 on page 11 for Recommended Operating Conditions) 1.8V 100 mV dc or 2.5V 100 mV 3.3V 165 mV (603 bus only)(1) (input thresholds are configuration pin selectable)
Packages
Core power supply
I/O power supply
Note:
1. 3.3V I/O bus not supported for 1.5V core power supply processor version.
3. Overview
This section summarizes features of the PC7410's implementation of the PowerPC architecture. Major features of the PC7410 are as follows: * Branch Processing Unit - Four instructions fetched per clock - One branch processed per cycle (plus resolving two speculations) - Up to one speculative stream in execution, one additional speculative stream in fetch - 512-entry Branch History Table (BHT) for dynamic prediction - 64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch delay slots * Dispatch Unit - Full hardware detection of dependencies (resolved in the execution units) - Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU) - Serialization control (predispatch, postdispatch, execution serialization) * Decode - Register file access - Forwarding control - Partial instruction decode
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* Completion - 8-entry completion buffer - Instruction tracking and peak completion of two instructions per cycle - Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization and all instruction flow changes * Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands - Fixed-point Unit 1 (FXU1): multiply, divide, shift, rotate, arithmetic, logical - Fixed-point Unit 2 (FXU2)--shift, rotate, arithmetic, logical - Single-cycle arithmetic, shifts, rotates, logical - Multiply and divide support (multi-cycle) - Early out multiply * Three-stage Floating-point Unit and a 32-entry FPR File - Support for IEEE-754 standard single- and double-precision floating-point arithmetic - Three-cycle latency, one-cycle throughput (single or double precision) - Hardware support for divide - Hardware support for denormalized numbers - Time deterministic non-IEEE mode * System Unit - Executes CR logical instructions and miscellaneous system instructions - Special register transfer instructions * AltiVec Unit - Full 128-bit data paths - Two dispatchable units: vector permute unit and vector ALU unit - Contains its own 32-entry 128-bit Vector Register File (VRF) with six renames - The vector ALU unit is further sub-divided into the Vector Simple Integer Unit (VSIU), the Vector Complex Integer Unit (VCIU) and the Vector Floating-point Unit (VFPU) - Fully pipelined * Load/Store Unit - One-cycle load or store cache access (byte, half-word, word, double-word) - Two-cycle load latency with one-cycle throughput - Effective address generation - Hits under misses (multiple outstanding misses) - Single-cycle unaligned access within double-word boundary - Alignment, zero padding, sign extend for integer register file - Floating-point internal format conversion (alignment, normalization) - Sequencing for load/store multiples and string operations - Store gathering - Executes the cache and TLB instructions - Big- and little-endian byte addressing supported - Misaligned little-endian supported
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- Supports FXU, FPU, and AltiVec load/store traffic - Complete support for all four architecture AltiVec DST streams * Level 1 (L1) Cache Structure - 32K 32-byte line, 8-way set associative instruction cache (iL1) - 32K 32-byte line, 8-way set associative data cache (dL1) - Single-cycle cache access - Pseudo Least-recently-used (LRU) replacement - Data cache supports AltiVec LRU and transient instructions algorithm - Copy-back or write-through data cache (on a page-per-page basis) - Supports all PowerPC memory coherency modes - Non-blocking instruction and data cache - Separate copy of data cache tags for efficient snooping - No snooping of instruction cache except for ICBI instruction * Level 2 (L2) Cache Interface - Internal L2 cache controller and tags; external data SRAMs - 512K, 1M and 2-Mbyte 2-way set associative L2 cache support - Copyback or write-through data cache (on a page basis or for all L2) - 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size - Supports pipelined (register-register) synchronous burst SRAMs and pipelined (registerregister) late-write synchronous burst SRAMs - Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM (either all, half or none of L2 SRAM must be configured as direct mapped - Core-to-L2 frequency divisors of /1, /1.5, /2, /2.5, /3, /3.5, and /4 supported - 64-bit data bus which also support 32-bits bus mode - Selectable interface voltages of 1.8V and 2.5V * Memory Management Unit - 128 entry, 2-way set associative instruction TLB - 128 entry, 2-way set associative data TLB - Hardware reload for TLBs - Four instruction BATs and four data BATs - Virtual memory support for up to four petabytes (252) of virtual memory - Real memory support for up to four gigabytes (232) of physical memory - Snooped and invalidated for TLBI instructions * Efficient Data Flow - All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are 128 bits wide - dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF - L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s - Up to eight outstanding out-of-order cache misses between dL1 and L2/bus - Up to seven outstanding out-of-order transactions on the bus
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- Load folding to fold new dL1 misses into older outstanding load and store misses to the same line - Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e., address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed) - Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1 - Separate additional queues for efficient buffering of outbound data (castouts, write throughs, etc.) from dL1 and L2 * Bus Interface - MPX bus extension to 60X processor interface - Mode-compatible with 60x processor interface - 32-bit address bus - 64-bit data bus - Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x supported - Selectable interface voltages of 1.8V, 2.5V and 3.3V * Power Management - Low-power design with thermal requirements very similar to PC740 and PC750 - Low voltage 1.8V or 1.5V processor core - Selectable interface voltages of 1.8V can reduce power in output buffers - Three static power saving modes: doze, nap, and sleep - Dynamic power management * Testability - LSSD scan design - IEEE 1149.1 JTAG interface - Array Built-in Self Test (ABIST) - factory test only - Redundancy on L1 data arrays and L2 tag arrays * Reliability and Serviceability - Parity checking on 60x and L2 cache buses
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4. Signal Description
Figure 4-1. PC7410 Microprocessor Signal Groups
L2OVDD GND L2AVDD
BR L2ADDR[0:18] L2DATA[0:63] L2DP[0:7]
1 1 1 1 32 4 5 1 3 1 1 1 1 1 1 1 1 1 64 8
Address Arbitration
13
49
1
19 64 8 1 1 1 2 1 1 1 1 1 1 1
BG ABB/AMON[0]
L2 Cache Address/Data
Address Start Address Bus
TS A[0:31] AP[0:3] TT[0:4] TBST TSIZ[0:2]
L2CE L2WE L2CLKOUTA, L2CLKOUTB L2SYNC_OUT L2SYNC_IN L2ZZ INT SMI MCP SRESET HRESET CKSTP_IN CKSTP_OUT HIT SHDO, SHD1 RSRV TBEN EMODE QREQ QACK DRDY SYSCLK PLL_CFG[0:3] CLK_OUT JTAG:COP Factory Test L1_TSTCLK, L2_TSTCLK BVSEL L2VSEL
L2 Cache Clock/Control
Transfer Attribute
GBL WT CI CHK AACK ARTRY DBG
PCX7410
1 1 1 1 2 1 1 1 1
Interrupts Reset
Address Termination
Data Arbitration
DBWO, DTI(0) DBB, DMON(0) D[0:63]
Processor Status Control
1 1 1 4
Data Transfer
DP[0:7] DTI(2) TA
Clock Control Test Interface LSSD_MODE I/O Voltage Selection
1 1 1 1 12 20 1
1 5 3
Data Termination
DTI1 TEA
1 1
VDD
OVDD
AVDD
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5. Detailed Specification
This specification describes the specific requirements for the microprocessor PC7410 in compliance with e2v standard screening.
6. Applicable Documents
1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: Appendix A: General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein.
6.1
6.1.1
Design and Construction
Terminal Connections Depending on the package, the terminal connections are as shown in Table 12-1 on page 33, Table 6-3 on page 11 and Figure 4-1 on page 8.
6.2
Absolute Maximum Ratings
Absolute Maximum Ratings(1)
Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage 60x bus supply voltage L2 bus supply voltage Processor bus input voltage L2 bus input voltage JTAG signal input voltage Storage temperature range Rework temperature Value -0.3 to 2.1(4) -0.3 to 2.1
(4) (4) (3)(6)
Table 6-1.
Symbol VDD AVDD L2AVDD OVDD L2OVDD VIN VIN VIN TSTG Notes:
Unit V V V V V V V V C C
-0.3 to 2.1
-0.3 to 3.465 -0.3 to 2.6(3)
-0.3 to OVDD + 0,2V(2)(5) -0.3 to L2OVDD + 0,2V -0.3 to OVDD + 0,2V -55 to 150 260
(2)(5)
1. Functional and tested operating conditions are given in Table 6-3 on page 11. Absolute maximum ratings are stress ratings only. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.2V at any time including during power-on reset. 3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0V at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4V at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 6-1 on page 10. 6. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a maximum value OVDD of -0.3 to 2.6V.
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Figure 6-1. Overshoot/Undershoot Voltage
(L2)OVDD + 20% (L2)OVDD + 5% (L2)OVDD
VIH
VIL GND GND - 0.3V
GND - 0.7V Not to exceed 10% of tSYSCLK
The PC7410 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The PC7410 "core" voltage must always be provided at nominal voltage (see Table 6-3 on page 11 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 6-2. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD or L2OVDD power pins. Table 6-2. Input Threshold Voltage Setting
Processor Bus Input Threshold is Relative to: 1.8V 2.5V 3.3V
(6) (7) (7)
BVSEL Signal 0(1) HRESET(1)(2) 1
(1)(4)(5)
L2VSEL Signal(3) 0 HRESET 1 HRESET
L2 Bus Input Threshold is Relative to: 1.8 2.5 2.5 Not supported
HRESET Notes:
3.3V
1. Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied. 2. To select the 2.5V threshold option, L2VSEL/BVSEL should be tied to HRESET so that the two signals change state together. This is the preferred method for selecting this mode operation. 3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 should be used. 4. Default voltage setting if left unconnected (internal pulled-up). Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD, the default voltage setting if left unconnected is 2.5V. 5. Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD, having BVSEL = 1 selects the 2.5V threshold. 6. Parts Rev 1.4 and later only. Previous revisions do not support BVSEL = HRESET. 7. NSpec does not support the default OVDD setting of 3.3V. The BVSEL input must be tie either low or HRESET.
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6.3 Recommended Operating Conditions
Recommended Operating Conditions(1)
Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage BVSEL = 0 Processor bus supply voltage see note
(3)
Table 6-3.
Symbol VDD AVDD L2AVDD OVDD OVDD OVDD
(2)(3)
Recommended Value 1.8 100 mV or 1.5 50 mV 1.8 100 mV or 1.5 50 mV 1.8 100 mV or 1.5 50 mV 1.8 100 mV 2.5 100 mV
(4)
Unit V V V V V V V V V V V C
BVSEL = HRESET BVSEL = 1 or = HRESET L2VSEL = 0
3.3 165 mV 1.8 100 mV
L2OVDD L2OVDD VIN VIN VIN TJ Notes:
L2 bus supply voltage
L2VSEL = 1
(2)
or L2VSEL = HRESET
2.5 100 mV GND to OVDD GND to L2OVDD GND to OVDD -55 to 125
Processor bus Input voltage L2 Bus JTAG Signals Die-junction temperature
1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a recommended OVDD value of 2.5V 100 mV for BVSEL = 1. 3. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL = HRESET. 4. Not supported for N spec with VDD = 1.5V
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7. Thermal Characteristics
7.1 Package Characteristics
Package Thermal Characteristics CBGA
Characteristic Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board(1)(2) Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board Junction-to-ambient thermal resistance, 400 ft/min airflow, single-layer (1s) board Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board Junction-to-ambient thermal resistance, 400 ft/min airflow, four-layer (2s2p) board Junction-to-board thermal resistance
(4) (1)(3) (1)(3)
Table 7-1.
Symbol RJA RJMA RJMA RJMA RJMA RJMA RJB RJC Notes:
Value PC7410 CBGA 24 17 18 16 14 13 8 < 0.1
Unit C/W C/W C/W C/W C/W C/W C/W C/W
(1)(3)
Junction-to-case thermal resistance(5)
1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of RJC for the part is less than 0.1C/W.
See "Thermal Management Information" on page 13 for more details about thermal management. The board designer can choose between several commercially available heat sink types to place on the PC7410. For exposed-die packaging technology as in Table 7-1, the intrinsic conduction thermal resistance paths are shown in Figure 7-1 on page 13. 7.1.1 Package Thermal Characteristics for HiTCE Table 7-2 provides the package thermal characteristics for the PC7410, HiTCE. Table 7-2. Package Thermal Characteristics for HiTCE Package
Value Characteristic Junction-to-bottom of balls
(1)
Symbol RJ R JMA RJB
PC7410 HiTCE 6.8 20.7 11.0
Unit
C/W C/W C/W
Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board(1)(2) Junction to board thermal resistance Notes: 1. Simulation, no convection air flow. 2. Per JEDEC JESD51-6 with the board horizontal.
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7.1.2 Package Thermal Characteristics for CI-CGA Table 7-3. Package Thermal Characteristics for CI-CGA
Value Characteristic Junction to board thermal resistance Symbol RJB PC7410 CI-CGA 8.42 Unit
C/W
7.2
Internal Package Conduction Resistance
Figure 7-1 depicts the primary heat transfer path for a package with an attached heat sink mounted on a printed circuit board. Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material) and finally to the heat sink where it is removed by forcedair convection. Since the silicon thermal resistance is quite small, for a first-order analysis the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. Figure 7-1. C4 Package with Heat Sink Mounted on a Printed Circuit Board
External Resistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Printed Circuit Board Die Junction Die/Package Package/Leads
External Resistance
Radiation
Convection
7.3
Thermal Management Information
This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design - the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package and mounting clip and screw assembly; see Figure 7-2 on page 14. This spring force should not exceed 5.5 pounds of force. Ultimately, the final selection of an appropriate heat sink depends on many factors such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly and cost.
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Figure 7-2. CBGA Package Cross-section with Heat Sink Options
Heat Sink Heat Sink Clip
Adhesive or Thermal Interface Material Option Printed-Circuit Board
7.3.1
Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 7-3 on page 15 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 7-2). This spring force should not exceed 5.5 pounds of force. Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure. The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet must have adequate mechanical strength to meet equipment shock/vibration requirements.
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Figure 7-3. Thermal Performance of Different Thermal Interface Materials
2 Silicone Sheet (0.006") Bare Joint Floroether Oil Sheet (0.007") Graphite/Oil Sheet (0.005") Synthetic Grease
Specific Thermal Resistance (K-in.2/W)
1.5
1
0.5
0 0 10 20 30 40 50 Contact Pressure (psi) 60 70 80
7.3.1.1
Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: T j = T a + T r + ( jc + int + sa ) x P d where: TJ = die-junction temperature Ta = inlet cabinet ambient temperature Tr = air temperature rise within the computer cabinet jc = junction-to-case thermal resistance int = adhesive or interface material thermal resistance sa = heat sink base-to-ambient thermal resistance Pd = power dissipated by the device During operation, the die-junction temperatures (TJ) should be maintained less than the value specified in Table 6-3 on page 11. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 C to 40 C. The air temperature rise within a cabinet (Tr) may be in the range of 5 C to 10 C. The thermal resistance of the thermal interface material ( int) is typically about 1 C/W. Assuming a Ta of 30 C, a Tr of 5 C, a CBGA package jc = 0.03, and a power consumption (Pd) of 5.0 watts, the following expression for TJ is obtained: T j = 30 C + 5 C + ( 0,03 C W + 1,0 C W + sa ) x 5W
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For a Thermally heat sink #2328B, the heat sink-to-ambient thermal resistance (sa) versus airflow velocity is shown in Figure 7-4. Figure 7-4. Thermalloy #2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow Velocity
8
7 Heat Sink Thermal Resistance (C/W)
Thermalloy #2328B Pin-Fin Heat Sink (25 x 28 x 15 mm)
6
5
4
3
2
1 0 0.5 1 1.5 2 2.5 Approach Air Velocity (m/s) 3 3.5
Assuming an air velocity of 0.5 m/s, the effective Rsa is 7 C/W, thus T J = 30 C + 5 C + ( 0,03 C W + 1,0 C W + 7 C W ) x 5W , resulting in a die-junction temperature of approximately 75 C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering and Aavid Engineering offer different heat sink-to-ambient thermal resistances and may or may not need air flow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure of merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final diejunction operating temperature is not only a function of the component-level thermal resistance, but of the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature - airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc.
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Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, it is recommended to use conjugate heat transfer models for the board, as well as system-level designs. To expedite system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM(R). These are available upon request.
8. Power Consideration
8.1 Power Management
The PC7410 provides four power modes, selectable by setting the appropriate control bits in the MSR and HIDO registers. The four power modes are: * Full-power: This is the default power state of the PC7410. The PC7410 is fully powered and the internal functional units are operating at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution or external hardware. * Doze: All the functional units of the PC7410 are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or machine check brings the PC7410 into the full-power state. The PC7410 in doze mode maintains the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the fullpower state takes only a few processor clock cycles. * Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The PC7410 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or a machine check input (MCP). A return to full-power state from a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is negated, the processor is put in doze mode to support snooping. * Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may disable the PLL and SYSCLK. Returning the PC7410 to the full-power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset or a machine check input (MCP) signal after the time required to relock the PLL.
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8.2 Power Dissipation
Table 8-1. Power Consumption for PC7410 (1.8V)
Processor (CPU) Frequency Power Mode Core power supply Full-On Mode Typical(1)(3) Maximum
(1)(2)(4)(5)
400 MHz 1.5V 1.8V 1.5V
450 MHz 1.8V
500 MHz 1.8 V Unit
2.92 6.6
4.2 9.5
3.29 7.43
4.7 10.7
5.3 11.9
W W
Doze Mode Maximum(1)(2)(5) Nap Mode Maximum(1)(2)(5) Sleep Mode Maximum(1)(2)(5) 1.3 1.3 1.45 1.45 1.6 W 1.35 1.35 1.5 1.5 1.65 W 3.6 4.3 4.1 4.8 5.3 W
Sleep Mode - PLL and DLL Disabled Typical(1)(3) Maximum Notes:
(1)(2)(5)
600 1.1
600 1.1
600 1.1
600 1.1
600 1.1
mW W
1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically <5% of VDD power. Worst case power consumption for AVDD = 15 mW and L2AVDD = 15 mW. 2. Maximum power is measured at 105C, at VDD = 1.8V or 1.5Vwhile running an entirely cache-resident, contrived sequence of instructions which keep the execution units, including AltiVec, maximally busy. 3. Typical power is an average value measured at 65C, VDD = 1.8V or 1.5V, OVDD = L2OVDD = 2.5V in a system while running a codec application that is AltiVec intensive. 4. These values include the use of AltiVec. Without AltiVec operation, estimate a 25% decrease. 5. Power consumption derating at low temperatures to be defined after device characterization.
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9. Electrical Characteristics
9.1 Static Characteristics
DC Electrical Specifications (see Table 6-3 on page 11 for Recommended Operating Conditions)
Characteristic Input high voltage (all inputs except SYSCLK)(2)(3)(8) Nominal Bus Voltage(1) 1.8 2.5 3.3 1.8 Input low voltage (all inputs except SYSCLK)(8) 2.5 3.3 1.8 SYSCLK input high voltage
(2)(8)
Table 9-1.
Symbol VIH VIH VIH VIL VIL VIL CVIH CVIH CVIH CVIL CVIL CVIL IIN IIN IIN ITSI ITSI ITSI VOH VOH VOH VOL VOL VOL CIN Note:
Min 0.65 x (L2)OVDD 1.7 2.0 -0.3 -0.3 -0.3 1.5 2.0 2.4 -0.3 -0.3 -0.3 - - - - - - (L2)OVDD - 0.45 1.7 2.4 - - - -
Max (L2)OVDD + 0.2 (L2)OVDD + 0.2 OVDD + 0.3 0.35 x (L2)OVDD 0.2 x (L2)OVDD 0.8 OVDD + 0.2 OVDD + 0.2 OVDD + 0.3 0.2 0.4 0.4 20 35 70 20 35 70 - - - 0.45 0.4 0.4 6.0
Unit
V
V
2.5 3.3 1.8
V
SYSCLK input low voltage(8)
2.5 3.3 1.8
V
Input leakage current, VIN = L2OVDD/OVDD(2)(3)(6)(7)
2.5 3.3 1.8
A
High-Z (off-state) leakage current, VIN = L2OVDD/OVDD(2)(3)(5)(7)
2.5 3.3 1.8
A
Output high voltage, IOH = -5 mA
(8)
2.5 3.3 1.8
V
Output low voltage, IOL = 5 mA(8)
(3)(4)(7)
2.5 3.3
V
Capacitance, VIN = 0V, f = 1 MHz
pF
1. Nominal voltages; see Table 6-3 on page 11 for recommended operating conditions. 2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals. 3. Excludes factory test signals. 4. Capacitance is periodically sampled rather than 100% tested. 5. The leakage is measured for nominal OVDD and L2OVDD, or both OVDD and L2OVDD must vary in the same direction (for example, both OVDD and L2OVDD vary by either +5% or -5%). 6. Measured at max OVDD/L2OVDD. 7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.
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8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL/VOH/CVIH/CVIL DC limits of 1.8V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed, there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a SAMPLE instruction, the DC voltage limits will be controlled by the BVSEL/L2VSEL settings during HRESET. Anytime HRESET is not asserted (i.e., just asserting TRST), the voltage mode is not known until either EXTEST or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8V.
9.2
Dynamic Characteristics
After fabrication, parts are sorted by maximum processor core frequency as shown in "Clock AC Specifications" and tested for conformance to the AC specifications for that frequency. These specifications are for valid processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency.
9.2.1
Clock AC Specifications Table 9-2 provides the clock AC timing specifications as defined in Figure 9-1 on page 21. Clock AC Timing Specifications (See Table 6-3 on page 11 for Recommended Operating Conditions)
Maximum Processor Core Frequency 400 MHz 450 MHz Min 350 700 33 7.5 Max 450 900 133 30 1.0 0.5 40 60 150 100 40 500 MHz Min 350 700 33 7.5 Max 500 1000 133 30 1 0.5 60 150 100 Unit MHz MHz MHz ns ns ns % ps s
Table 9-2.
Symbol fCORE(1) fVCO
(1)
Characteristic Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time
Min 350 700 33 7.5
Max 400 800 133 30 1.0 0.5
fSYSCLK(1) tSYSCLK tKR & tKR & tKF(2) tKF(3)
tKHKL/tSYSCLK(4)
SYSCLK duty cycle measured at OVDD/2 SYSCLK jitter
(5) (6)
40
60 150 100
Internal PLL relock time Note:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in "Clock Selection" on page 42 for valid PLL_CFG[0:3] settings. 2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OVDD = 3.3V nominal. 3. Rise and fall times for the SYSCLK input measured from 0.2V to 1.2V when OVDD = 1.8V or 2.5V nominal. 4. Timing is guaranteed by design and characterization. 5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design. 6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
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Figure 9-1. SYSCLK Input Timing Diagram
tSYSCLK tKHKL SYSCLK VM VM VM CVIH CVIL tKR
tKF
Note:
VM = Midpoint Voltage (OVDD/2).
9.2.2
Processor Bus AC Specifications Table 9-3 provides the processor AC timing specifications for the PC7410 as defined in Figure 9-3 on page 23 and Figure 9-4 on page 24. Timing specifications for the L2 bus are provided in "L2 Bus AC Specifications" on page 26. Processor Bus AC Timing Specifications(1) at VDD = AVDD = 1.8V 100 mV; -55C TJ 125C, OVDD = 1.8V 100 mV
400, 450, 500 MHz Parameter Input Setup Input Hold Output Valid Times: TS ARTRY/SHD0/SHD1 All Other Outputs
(7)(8)
Table 9-3.
Symbol tIVKH tIXKH tKHTSV tKHARV tKHOV tKHTSX tKHARX tKHOX tKHOE(11) tKHOZ
(2)
Min 1.0 0 - - - 0.5 0.5 0.5 0.5 - - -
Max - - 3.0 2.3 3.0 - - - - 3.5 1 1
Unit ns ns
ns
Output Hold Times:(7)(12) TS ARTRY/SHD0/SHD1 All Other Outputs SYSCLK to Output Enable SYSCLK to Output High Impedance (all except ABB/AMON[0], ARTRY/SHD, DBB/DMON[0]), SHD0, SHD1) SYSCLK to ABB/AMON[0], DBB/DMON[0] High Impedance after precharge Maximum Delay to ARTRY/SHD0/SHD1 Precharge
ns
ns ns tSYSCLK tSYSCLK
tKHABPZ(5)(9)(11) tKHARP(5)(10)(11) Note:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings assume a purely resistive 50 load (see Figure 9-3 on page 23). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). 3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 9-4 on page 24).
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4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence. 5. tSYSCLK is the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3]. 7. All other output signals are composed of the following - A[0:31], AP[0:3], TT[0:4], TBST, TSIZ[0:2], GBL, WT, CI, DH[0:31], DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV. 8. Output valid time is measured from 2.4V to 0.8V which may be longer than the time required to discharge from VDD to 0.8V. 9. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low then precharged high before returning to high-Z as shown in Figure 9-2 on page 23. The nominal precharge width for ABB or DBB is 0.5 x tSYSCLK, i.e., less than the minimum tSYSCLK period, to ensure that another master asserting ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is guaranteed by design. 10. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK ; i.e., it should be high-Z as shown in Figure 9-2 on page 23 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing are tested for the signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design. 11. Guaranteed by design and not tested. 12. Output hold time characteristics can be altered by the use of the L2_TSTCK pin during system reset, similar to L2 output hold being altered by the use of bits [14-15] in the L2CR register. Information on the operation of the L2_TSTCLK will be included in future revisions of this specification.
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Figure 9-2. Input/Output Timing Diagram
VM VM VM
SYSCLK tIVKH tIXKH All Inputs
All Outputs (except TS, ABB, ARTRY, DBB)
tKHOV
tKHOX
All Outputs (except TS, ABB, ARTRY, DBB)
tKHOE
tKHOZ
tKHABPZ TS, ABB/AMON[0], DBB/DMON[0] tKHTSV tKHTSV tKHTSX
tKHARPZ tKHARP ARTRY, tKHARV SHD0, SHD1 tKHARX tKHARV
VM = Midpont Voltage (OVDD/2)
Figure 9-3.
AC Test Load for the 60x Interface
Output Z0 = 50 RL = 50 OVDD/2
Figure 9-4 on page 24 provides the mode select input timing diagram for the PC7410. The mode select inputs are sampled twice, once before and once after HRESET negation.
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Figure 9-4. Mode Input Timing Diagram
VM VM
SYSCLK
HRESET
Mode Signals First sample Second sample
where VM = Midpoint Voltage (OVDD/2) 9.2.3 L2 Clock AC Specifications The L2CLK frequency is programmed by the L2 configuration register (L2CR[4:6]) core-to-L2 divisor ratio. See Table 13-2 on page 43 for example core and L2 frequencies at various divisors. Table 9-4 on page 25 provides the potential range of L2CLK output AC timing specifications as defined in Figure 9-5 on page 26. The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN input of the PC7410 to synchronize L2CLKOUT at the SRAM with the processor's internal clock. L2CLKOUT at the SRAM can be offset forward or backward in time by shortening or lengthening the routing of L2SYNC_OUT to L2SYNC_IN. See FreescaleTM Application Note AN179/D "PowerPC Backside L2 Timing Analysis for the PCB Design Engineer." The minimum L2CLK frequency of Table 9-4 is specified by the maximum delay of the internal DLL. The variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned with the PC7410 core clock at the SRAMs. The maximum L2CLK frequency shown in Table 9-4 is the core frequency divided by one. Very few L2 SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK frequency for any application of the PC7410 will be a function of the AC timings of the PC7410, the AC timings for the SRAM, bus loading and printed circuit board trace length. e2v is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part on a functional tester at the maximum frequencies of Table 9-4. Therefore, functional operation and AC timing information are tested at core-to-L2 divisors of 2 or greater. L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC timings of Table 9-5 on page 26 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. However, since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals of Table 9-5 are referenced to this signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually measured relative to SYSCLK.
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Table 9-4.
L2CLK Output AC Timing Specifications at Recommended Operating Conditions (See Table 6-3 on page 11)
400 MHz 450 MHz Min 133 2.5 50 640 10 50 150 0 10 50 150 640 0 Max 400 7.5 500 MHz Min 133 2.5 50 10 50 150 Max 400 7.5 Unit MHz ns % L2CLK ns ps ps
Symbol fL2CLK(1)(4) tL2CLK tCHCL/tL2CLK(2)
Parameter L2CLK frequency L2CLK cycle time L2CLK duty cycle Internal DLL-relock time DLL capture window(5)
(3)
Min 133 2.5 50 640 0 -
Max 400 7.5
tL2CSKW
L2CLKOUT output-to-output skew(6) L2CLKOUT output jitter(6)
Note:
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. The maximum L2LCK frequency will be system-dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading. 2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization. 4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL. 5. Allowable skew between L2SYNC_OUT and L2SYNC_IN. 6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis.
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Figure 9-5.
L2CLK_OUT Output Timing Diagram
L2 Single-Ended Clock Mode
tL2CLK tCHCL L2CLK_OUTA VM VM VM tL2CR tL2CF
L2CLK_OUTB
VM
VM
VM tL2CSKW
L2SYNC_OUT
VM
VM
VM
VM
L2 Differential Clock Mode
tCHCL L2CLK_OUTB L2CLK_OUTA VM
tL2CLK
VM
VM
L2SYNC_OUT
VM
VM
VM
Note:
VM = Midpoint Voltage (L2OVDD/2)
9.2.4
L2 Bus AC Specifications Table 9-5 provides the L2 bus interface AC timing specifications for the PC7410 as defined in Figure 9-6 on page 27 and Figure 9-7 on page 28 for the loading conditions described in Figure 9-8 on page 28. L2 Bus Interface AC Timing Specifications at VDD = AVDD = L2AVDD = 1.8V 100mV or 1.5V 50mV ; -55C TJ 125C, L2OVDD = 2.5V 100mV or L2OVDD = 1.8V 100mV
400, 450, 500 MHz Parameter L2SYNC_IN rise and fall time Setup Times Data and parity Input Hold Times Data and parity 1.5 0.0 Min Max 1.0 Unit ns ns ns
Table 9-5.
Symbol tL2CR & tL2CF(1) tDVL2CH(2) tDXL2CH(2)
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Table 9-5. L2 Bus Interface AC Timing Specifications at VDD = AVDD = L2AVDD = 1.8V 100mV or 1.5V 50mV ; -55C TJ 125C, L2OVDD = 2.5V 100mV or L2OVDD = 1.8V 100mV (Continued)
400, 450, 500 MHz Symbol Parameter Valid Times All outputs when L2CR[14:15] = 00 All outputs when L2CR[14:15] = 01 All outputs when L2CR[14:15] = 10 All outputs when L2CR[14:15] = 11 Output Hold Times All outputs when L2CR[14:15] = 00 All outputs when L2CR[14:15] = 01 All outputs when L2CR[14:15] = 10 All outputs when L2CR[14:15] = 11 L2SYNC_IN to high impedance All outputs when L2CR[14:15] = 00 All outputs when L2CR[14:15] = 01 All outputs when L2CR[14:15] = 10 All outputs when L2CR[14:15] = 11 1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD. 2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN (see Figure 9-6). Input timings are measured at the pins. 3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 9-8 on page 28). 4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous burst RAMs, L2CR[14:15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14:15] = 10 is recommended. 0.4 0.8 1.2 1.6 2.0 2.5 3.0 3.5 Min Max 2.5 2.5 2.9 3.5 Unit
tL2CHOV
(3)(4)
ns
tL2CHOX
(3)
ns
tL2CHOZ
ns
Note:
Figure 9-6.
L2 Bus Input Timing Diagram
tL2CR tL2CF
L2SYNC_IN tDVL2CH L2 Data and Data Parity Inputs
VM
tDXL2CH
Note:
VM = Midpoint Voltage (L2OVDD/2)
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Figure 9-7. L2 Bus Output Timing Diagram
L2SYNC_IN
VM
VM
tL2CHOV tL2CHOX All Outputs
tL2CHOZ L2DATA BUS
Note:
VM = Midpoint Voltage (L2OVDD/2)
Figure 9-8.
AC Test Load for the L2 Interface
Output Z0 = 50 RL = 50 L2OVDD/2
9.2.5
IEEE 1149.1 AC Timing Specifications Table 9-6 provides the IEEE(R) 1149.1 (JTAG) AC timing specifications as defined in Figure 9-9 on page 29, Figure 9-10 on page 29, Figure 9-11 on page 29 and Figure 9-12 on page 30. Table 9-6.
Symbol fTCLK t TCLK tJHJL tJR & tJF tTRST(2) tDVJH(3) tIVJH tDXJH(3) tIXJH tJLDV(4) tJLOV tJLDZ(4)(5) tJLOZ(5)
JTAG AC Timing Specifications (Independent of SYSCLK) (1)at Recommended Operating Conditions (see Table 6-3 on page 11)
Parameter TCK frequency of operation TCK cycle time TCK clock pulse width measured at OVDD/2 TCK rise and fall times TRST assert time Input Setup Times: Boundary-scan data TMS, TDI Input Hold Times: Boundary-scan data TMS, TDI Valid Times: Boundary-scan data TDO TCK to output high impedance: Boundary-scan data TDO Min 0 30 15 0 25 4 0 20 25 4 4 3 3 20 25 19 9 2 Max 33.3 Unit MHz ns ns ns ns ns
ns
ns
ns
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Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 9-9). Time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 3. Non-JTAG signal input timing with respect to TCK. 4. Non-JTAG signal output timing with respect to TCK. 5. Guaranteed by design and characterization.
Figure 9-9.
Alternate AC Test Load for the JTAG Interface
Output Z0 = 50 RL = 50 OVDD/2
Figure 9-10. JTAG Clock Input Timing Diagram
tJR TCLK VM tJHJL VM
VM
tJF
tTCLK
Note:
VM = Midpoint Voltage (OVDD/2)
Figure 9-11. TRST Timing Diagram
tTRST
VM
TRST
VM
Note:
VM = Midpoint Voltage (OVDD/2)
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Figure 9-12. Boundary-scan Timing Diagram
TCK
VM VM
Boundary Data Inputs
tJLDV tJLDX
tDVJH
Input Data Valid
tDXJH
Boundary Data Outputs
Output Data Valid
tJLDZ
Boundary Data Outputs
Output Data Valid
Note:
VM = Midpoint Voltage (OVDD/2)
Figure 9-13. Test Access Port Timing Diagram
VM VM
TCK
tIVJH
tIXJH
Input Data Valid
TDI, TMS
tJLOV tJLOX
TDO
Output Data Valid
tJLOZ
TDO
Output Data Valid
Note:
VM = Midpoint Voltage (OVDD/2)
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10. Preparation for Delivery
10.1 Handling
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of static buildup. However, the following handling practices are recommended: * Devices should be handled on benches with conductive and grounded surfaces * Ground test equipment, tools and operator * Do not handle devices by the leads * Store devices in conductive foam or carriers * Avoid use of plastic, rubber or silk in MOS areas * Maintain relative humidity above 50% if practical * For CI-CGA packages, use specific tray to take care of the highest height of the package compared with the normal CBGA
11. Package Mechanical Data
11.1 Parameters
The package parameters are as provided in the following list. The package type is 25x25 mm, 360-lead CBGA, HiTCE and CI-CGA. Table 11-1.
Parameter Package outline Interconnects Pitch Minimum module height Maximum module height Ball or column diameter 25 mm x 25 mm 360 (19 x 19 ball array minus one) 1.27 mm (50 mil) 2.65 mm (CBGA, HiTCE), 3.65 mm (CI-CGA) 3.20 mm (CBGA), 3.24 mm (HiTCE), 4.20 mm (CI-CGA) 0.89 mm (35 mil)
Package Parameters
The following remarks apply to Figure 12-7 on page 39 and Figure 12-9 on page 41: * Dimensions and tolerancing are as per ASME Y14.5M-1994. * All dimensions are in millimeters. * Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array. * Dimension B is the maximum solder ball diameter measured parallel to datum A. * D2 and E2 define the area occupied by the die and underfill. Actual size of this area may be smaller than shown. D3 and E3 are the minimum clearance from the package edge to the chip capacitors.
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12. Pin Assignments
12.1 BGA360 Package
Figure 12-1, Figure 12-2, Figure 12-3 on page 33 and Figure 12-4 on page 33 show top views of the packages available for the PC7410. Note that these drawings are not to scale. Figure 12-1. Top View of 360-Ball CBGA and 360-Pin CI-CGA Packages
Pin A1 Index
Figure 12-2. Top View of 360-pin CBGA and CI-CGA Packages
1 A B C D E F G H J K L M N P R T U V W 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
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Figure 12-3. Cross-section of 360-ball CBGA and HiTCE Package
Substrate Assembly Encapsulant View Die
Figure 12-4. Cross-section of 360-column CI-CGA Package
Substrate Assembly Encapsulant View Die
Table 12-1.
Signal Name A[0:31] AACK ABB AMON[0](12) AP[0:3] ARTRY AVDD BG BR
(12)
Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages
Pin Number A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2 N3 L7 C4, C5, C6, C7 L6 A8 H1 E7 W1 K11 C2 B8 D7 E3 K5 K1 Low Low High Low Low Low Low High Low Low Input Output Input Input I/O Input Output Output Output Input Active High Low Low High Low I/O I/O Input Output I/O I/O I/F Select(1) BVSEL BVSEL BVSEL BVSEL BVSEL VDD BVSEL BVSEL N/A BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
BVSEL(1)(3)(8)(9)(14) CHK CI CKSTP_IN CKSTP_OUT CLK_OUT DBB DMON[0](12) DBG
(12) (4)(8)(9)
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Table 12-1.
Signal Name DH[0:31]
Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued)
Pin Number W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3, U4, R5 M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3, U3, W2 L1, P2, M2, V2, M1, N2, T3, R1 K9 D1 H6, G1 A3 B1 D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16 B5 B6 C11
(2)
Active High
I/O I/O
I/F Select(1) BVSEL
DL[0:31] DP[0:7] DRDY(6)(8)(13) DBWO DTI[0] DTI[1:2](10)(13) EMODE(7)(10) GBL
High High Low Low High Low Low
I/O I/O Output Input Input Input I/O
BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL
GND
N/A
HIT(6)(8) HRESET INT L1_TSTCLK
Low Low Low High High High
Output Input Input Input Output Output
BVSEL BVSEL BVSEL BVSEL L2VSEL L2VSEL VDD
F8 L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17, J14, J13, H19, G18 K19, W19 L13 P17 N15 L16 U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14, E13 V14, U16, T19, N18, H14, F17, C19, B15 D15, E14, E16, H16, J15, L15, M16, K13, P15, R14, R16, T15, F15 L14 M14 F7 A19
L2ADDR[0:16] L2ADDR[17:18](8) L2AVDD L2CE L2CLKOUTA L2CLKOUTB
Low High High
Output Output Output
L2VSEL L2VSEL L2VSEL
L2DATA[0:63]
High
I/O
L2VSEL
L2DP[0:7] L2OVDD(11) L2SYNC_IN L2SYNC_OUT L2_TSTCLK(2) L2VSEL
(1)(3)(8)(9)(14)
High
I/O
L2VSEL N/A
High High High High
Input Output Input Input
L2VSEL L2VSEL BVSEL N/A
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Table 12-1.
Signal Name L2WE L2ZZ LSSD_MODE MCP OVDD PLL_CFG[0:3] QACK QREQ RSRV SHD0(8) SHD1 SMI SRESET SYSCLK TA TBEN TBST TCK TDI
(9) (5)(8) (2)
Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued)
Pin Number N16 G17 F9 B11 D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9, R11, T5, T8, T12 A4, A5, A6, A7 B2 J3 D3 B3 B4 A12 E10 H9 F1 A2 A11 B10 B7 D9 J1 C8 A10 K7 A9, B9, C9 C10, D11, B12, C12, F11 C3 G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 Low High Low High High High Low High Low Low High High Low High Low Low Low Low Low Low Low Input Input Output Output I/O I/O Input Input Input Input Input Output Input Input Output Input Input Input I/O Output I/O I/O Active Low High Low Low I/O Output Output Input Input I/F Select(1) L2VSEL L2VSEL BVSEL BVSEL N/A BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL BVSEL N/A
TDO TEA TMS(9) TRST TS TSIZ[0:2] TT[0:4] WT VDD Notes:
(9)(14)
1. OVDD supplies power to the processor bus, JTAG and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:18], L2ASPARE, L2DATA[0:63], L2DP[0:7] and L2SYNC_OUT) and the L2 control signals and VDD supplies power to the processor core and the PLL and DLL (after filtering to become AVDD and L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL/L2VSEL pin configurations of Table 6-2 on page 10 and the voltage supplied. For actual recommended value of VIN or supply voltages, see Table 6-3 on page 11. 2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
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3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD (selects 2.5V), GND (selects 1.8V), or to HRESET (selects 2.5V). The PC7410 Both the 60x processor bus and the L2 bus only support the 1.8 and 2.5 options (see Table 6-2 on page 10). the default selection if BVSEL and/or L2VSEL is left unconnected is 2.5V. 4. Connect to HRESET to trigger post power-on-reset (por) internal memory test. 5. Ignored in 60x bus mode. 6. Unused output in 60x bus mode. 7. Deasserted (pulled high) at HRESET for 60x bus mode. 8. Uses one of 9 existing no-connects in PC750's 360-ball BGA package. 9. Internal pull-up on die. 10. Reuses PC750's DRTRY, DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively). 11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OVDD pin on the PC7410 packages. 12. Output only for PC7410, was I/O for PC750. 13. Enhanced mode only. 14. To overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less than 250 should be used.
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Figure 12-5. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball CBGA Package
2X 0.2
A1 CORNER D D2 D3 C5-1 C5-2 C6-2 C6-1 C1-1 12X J2 C1-2 C 0.15 A 0.25 A E E2 E3 C4-1 C4-2 L2 L1 0.35 A A
Millimeters DIM A A1 A2 A3 A4 b D D2 D3 e E E2 E3 J1 J2 J3 K1 K2 L1 L2 MAX 3,2 1 1,3 0,6 0,82 0,9 0,82 0,93 25 BSC 10 typ 6,32 1,27 BSC 25 BSC 12,6 typ 8,26 0,89 BSC 3,2 BSC 0,68 BSC 6,56 8,13 8,61 7,04 MIN 2,72 0,8 1,1
2X 0.2
B
12X 12X J3 C3-1 C3-2 J1
C2-2 C2-1 K2 K1
1 2 3 4 5 6 7 8 9 10 11 1213141516 171819 W V U T R P N M L K J H G F E D C B A
A3 A2 A4 A1 A
Package Caps C1-1 C1-2 C2-1
Value F 0.01
Voltage Reference L2OVDD GND L2OVDD GND VDD GND OVDD GND OVDD GND VDD GND
e 360X B 0.3 CAB
C2-2 C3-1 C3-2 C4-1 C4-2 C5-1 C5-2 C6-1 C6-2
0.01
0.15 C
0.01
0.01
0.01
0.01
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters 3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array
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12.2 Substrate Capacitors for the PC7410
Figure 12-6 shows the connectivity of the substrate capacitor pads for the PC7410, 360 CBGA package. Figure 12-6. Substrate Bypass Capacitors for the PC7410
A1 CORNER C6-2 C6-1 Package Caps C1-1 C1-2 Value F Voltage Reference
C1-1 C1-2 C2-1 C2-2 C3-1 C3-2
C5-1 C5-2
0.01 0.01 0.01 0.01 0.01 0.01
L2OVDD GND L2OVDD GND VDD GND OVDD GND OVDD GND
VDD GND
C4-1 C4-2 L2 L1
C4-1 C4-2 C5-1
C2-2 C2-1 C3-1 C3-2
C5-2 C6-1 C6-2
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Figure 12-7. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball HiTCE Package
2X 0.2
A1 CORNER D D2 D3 C5-1 C5-2 C6-2 C6-1 C1-1 12X J2 C1-2 C 0.15 A 0.25 A E E2 C4-1 E3 C4-2 L2 L1 0.35 A A
Millimeters DIM A A1 A2 A3 A4 b D D2 D3 e E E2 E3 J1 J2 J3 K1 K2 L1 L2 MAX 3,2 1 1,3 0,6 0,82 0,9 0,82 0,93 25 BSC 10 typ 6,32 1,27 BSC 25 BSC 12,6 typ 8,26 0,89 BSC 3,2 BSC 0,68 BSC 6,56 8,13 8,61 7,04 MIN 2,72 0,8 1,1
2X 0.2
B
12X 12X J3 C3-1 C3-2 J1
C2-2 C2-1 K2 K1
1 2 3 4 5 6 7 8 9 10 11 1213141516 171819 W V U T R P N M L K J H G F E D C B A
A3 A2 A4 A1 A
Package Caps C1-1 C1-2 C2-1
Value F 0.01
Voltage Reference L2OVDD GND L2OVDD GND VDD GND OVDD GND OVDD GND VDD GND
e 360X B 0.3 CAB
C2-2 C3-1 C3-2 C4-1 C4-2 C5-1 C5-2 C6-1 C6-2
0.01
0.15 C
0.01
0.01
0.01
0.01
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters 3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array
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12.3 Substrate Capacitors for the PC7410
Figure 12-8 shows the connectivity of the substrate capacitor pads for the PC7410, 360 HITCE package. Figure 12-8. Substrate Bypass Capacitors for the PC7410
A1 CORNER C6-2 C6-1 Package Caps C1-1 C1-2 Value F Voltage Reference
C1-1 C1-2 C2-1 C2-2 C3-1 C3-2
C5-1 C5-2
0.01 0.01 0.01 0.01 0.01 0.01
L2OVDD GND L2OVDD GND VDD GND OVDD GND OVDD GND
VDD GND
C4-1 C4-2 L2 L1
C4-1 C4-2 C5-1
C2-2 C2-1 C3-1 C3-2
C5-2 C6-1 C6-2
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Figure 12-9. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-column CI-CGA Package
2X PIN A1 INDEX D 0.2 B
360X
2X 0.15
A
C6
2 1
C1
A3 A4
0.15 A
C5
0.35 A
E2
E4
21 21
C4
1 1
C2
2 2
E
C3
1 2
2X 0.2 C E3
D4 D3 D2 TOPVIEW
D1
1 2 3 4 5 6 7 8 9 10 11 1213141516 171819 W V U T R P N M L K J H G F E D C B A A2 A1 A
E1
K
G
K
GND : C1.2 C2.2 C3.2 C4.2 C5.2 C6.2 C1.1, C2.1 : L2OVDD
0.3 0.15
360X
B
T
T
E
F C3.1, C6.1 : OVDD
C4.1, C5.1 : OVDD
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13. Clock Selection
The PC7410's PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the PC7410 is shown in Table 13-1 for example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the minimum and maximum core frequencies listed in Table 9-3 on page 21. Table 13-1. PC7410 Microprocessor PLL Configuration(1)(2)(3)(4)(5)
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0:3] 0100 0110 1000 1110 1010 0111 1011 1001 1101 0101 0010 0001 1100 0000 0011 1111 Notes: Bus-toCore Multiplier 2x 2.5x 3x 3.5x 4x 4.5x 5x 5.5x 6x 6.5x 7x 7.5x 8x 9x Core-toVCO Multiplier 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 350 (700) 375 (750) 400 (800) 450 (900) PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied PLL off, no core clocking occurs 366 (733) 400 (800) 433 (866) 466 (933) 500 (1000) 375 (750) 412 (825) 450 (900) 488 (967) 375 (750) 416 (833) 458 (916) 500 (1000) 350 (700) 400 (800) 450 (900) 500 (1000) 400 (800) 465 (930) Bus 33.3 MHz Bus 50 MHz Bus 66.6 MHz Bus 75 MHz Bus 83.3 MHz Bus 100 MHz Bus 133 MHz
PLL off/bypass PLL off
1. PLL_CFG[0:3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the PC7410; see "Clock AC Specifications" on page 20 for valid SYSCLK, core, and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use and third- party emulator tool development only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In PLL-off mode, no clocking occurs inside the PC7410 regardless of the SYSCLK input. 5. PLL-off mode should not be used during chip power-up sequencing.
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The PC7410 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the PC7410. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL) circuit and should be routed from the PC74107410 to the external RAMs. A separate clock output, L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus interface. The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the PC7410 core, and the phase adjustment range that the L2 DLL supports. Table 13-2 shows various example L2 clock frequencies that can be obtained for a given set of core frequencies. The minimum L2 frequency target is 133 MHz. Sample core-to-L2 frequencies for the PC7410 is shown in Table 13-2. In this example, shaded cells represent settings that, for a given core frequency, result in L2 frequencies that do not comply with the minimum and maximum L2 frequencies listed in Table 9-6 on page 28. Table 13-2. Sample Core-to-L2 Frequencies
/1 350 366 400 - - - - /1.5 233 244 266 288 300 311 333 /2 175 183 200 216 225 233 250 /2.5 140 147 160 173 180 186 200 /3 - - 133 144 150 155 166 /3.5 - - - - - 133 143 /4 - - - - - - -
Core Frequency in MHz 350 366 400 433 450 466 500 Note:
The core and L2 frequencies are for reference only. Some examples may represent core or L2 frequencies which are not useful, not supported or not tested for by the PC7410; see "L2 Clock AC Specifications" on page 24 for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz.
14. System Design Information
14.1 PLL and DLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the PC7410 to supply power to the PLL and DLL, respectively. Both AVDD and L2AVDD can be supplied power from the VDD power plane. High frequency noise in the 500 kHz to 10 MHz resonant frequency range of the PLL on the VDD power plane could affect the stability of the internal clocks. On systems that use the PC7410 HCTE device, the AVDD and L2AVDD input signals should both implement the circuit shown in Figure 14-1 on page 44. On systems that use the PC7410 CBGA device, the L2AVDD input should implement the circuit shown in Figure 14-1.
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When selecting which filter to use on the AVDD input of the PC7410 CBGA device specifically, system designers should refer to Erratum No. 18 in the PC7410 RISC Microprocessor Chip Errata (MPC7410CE). The AVDD input of the PC7410 CBGA device is sensitive to system noise on both the VDD power plane, as described above, and the OVDD power plane as described in the Erratum No. 18. With these AVDD sensitivities to OVDD and VDD noise, care must be taken when selecting the filter circuit for the AVDD input of the PC7410 CBGA device. Erratum No. 18 does not apply to the AVDD input of the MPC7401 HCTE device, nor does it affect the L2AVDD input of either the HCTE or the CBGA device. As described in Erratum No. 18, when there is a high amount of noise on the OVDD power plane due to I/O switching rates, it is possible for the OVDD noise to couple into the PLL supply voltage (AVDD) internal to the PC7410 CBGA package. It is the recommendation of Freescale, that new designs using the PC7410 CBGA package provide the ability to implement either filter shown in Figure 14-1 and Figure 142 at the AVDD input. Existing designs that implemented Figure 14-1 on AVDD may never experience the error described in Erratum No. 18. Both new and existing designs should qualify both AVDD filter solutions, and the filter providing the most robust margin should be implemented. Figure 14-1. PLL Power Supply Filter Circuit No.1
10 VDD 2.2 F GND 2.2 F
Low ESL surface mount capacitor
AVDD (or L2AVDD)
Figure 14-2. PLL Power Supply Filter Circuit No.2
51 VDD AVDD Capacitor Pad Sites GND
The filter circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits. A separate circuit should be placed as close as possible to the L2AVDD pin. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 CBGA footprint, without the inductance of vias. The L2AVDD pin may be more difficult to route, but is proportionately less critical. It is the recommendation of Freescale, that systems that implement the AVDD filter shown in Figure 14-2 design in the pads for the removed capacitors (shown in Figure 14-1), to provide for the possible reintroduction of the filter in Figure 14-1. This would be necessary in case there is a planned transition from the CBGA package to the HiTCE package of the PC7410.
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14.2 Power Supply Voltage Sequency
The notes in Table 6-1 on page 9 contain cautions about the sequencing of the external bus voltages and core voltage of the PC7410 (when they are different). These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward-biased and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, one or both of the circuits of Figure 14-3 can be added to meet these requirements. The MUR420 Schottky diodes of Figure 14-3 control the maximum potential difference between the external bus and core power supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on power-down. Figure 14-3. Example Voltage Sequencing Circuits
2.5V MUR420 MUR420 1.8V
1N5820
1N5820
14.3
Decoupling Recommendations
Due to the PC7410's dynamic power management feature, large address and data buses and high operating frequencies, the PC7410 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PC7410 system and the PC7410 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and L2OVDD pin of the PC7410. It is also recommended that these decoupling capacitors receive their power from separate VDD, (L2)OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.01 F or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling PowerPC microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, L2OVDD, and OVDD planes to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100 - 330 F (AVX TPS tantalum or Sanyo OSCON).
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14.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND pins of the PC7410. See "L2 Clock AC Specifications" on page 24 for a discussion of the L2SYNC_OUT and L2SYNC_IN signals.
14.5
Output Buffer DC Impedance
The PC7410 60x and L2 I/O drivers are characterized over process, voltage and temperature. To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 14-4). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then Z0 = (RP + RN)/2. Figure 14-4 describes the driver impedance measurement circuit described above. Figure 14-4. Driver Impedance Measurement Circuit
OVDD
RN
SW2 Pad Data SW1
RP
OGND
Alternately, the following is another method to determine the output impedance of the PC7410. A voltage source, Vforce, is connected to the output of the PC7410, as in Figure 14-4. Data is held low, the voltage source is set to a value that is equal to (L2)OVDD/2, and the current sourced by Vforce is measured. The voltage drop across the pull-down device, which is equal to (L2)OVDD/2, is divided by the measured current to determine the output impedance of the pull-down device, RN. Similarly, the impedance of the pullup device is determined by dividing the voltage drop of the pull-up, (L2)OVDD/2, by the current sank by the pull-up when the data is high and Vforce is equal to (L2)OVDD/2. This method can be employed with either empirical data from a test setup or with data from simulation models, such as IBIS.
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RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. Figure 14-5 describes the alternate driver impedance measurement circuit. Figure 14-5. Alternate Driver Impedance Measurement Circuit
(L2)OVDD
BGA Pin Data
Vforce
OGND
Table 14-1 summarizes the signal impedance results. The driver impedance values were characterized at 0, 65, and 105C. The impedance increases with junction temperature and is relatively unaffected by bus voltage. Table 14-1. Impedance Characteristics with VDD = 1.8V, OVDD = 2.5V, TJ = 0 C - 105 C
Processor bus 41.5 - 54.3 37.3 - 55.3 L2 Bus 42.7 - 54.1 39.3 - 50 Symbol Z0 Z0 Unit
Impedance RN RP
14.6
Pull-up Resistor Requirements
The PC7410 requires pull-up resistors (1 k - 5 k) on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PC7410 or other bus masters. These pins are: TS, ARTRY, SHDO, SHD1. Four test pins also require pull-up resistors (100 - 1 k). These pins are CHK, L1_TSTCLK, L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal machine operation. If pull-down resistors are used to configure BVSEL or L2VSEL, the resistors should be less than 250. (see Table 12-1 on page 33). Because PLL_CFG[0:3] must remain stable during normal operation, strong pull-up and pull-down resistors (1 k or less) are recommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise or noise coupling. In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 k-5 k) if it is used by the system. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (1 k- 5 k) to prevent erroneous assertions of this signal.
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During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Since the PC7410 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the PC7410 or by other receivers in the system. These signals can be pulled up through weak (10 k) pull-up resistors by the system, address bus driven mode can be enabled (see the PC7410 RISC Microporcessor Family Users' Manual for more information on this mode), or these signals may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], CI, WT, and GBL. In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction while not driving GBL to the processor, we recommend that a strong (1 k) pull-up resistor be used on GBL. Note that the PC7410 will only snoop transactions when GBL is asserted. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If parity checking is disabled through HID0, and parity generation is not required by the PC7410 (note that the PC7410 always generates parity), then all parity pins may be left unconnected by the system. The L2 interface does not normally require pull-up resistors.
14.7
JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during poweron reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 14-6 on page 50 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0 isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the COP header be designed into the system as shown in Figure 14-6, if this is not possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.
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The COP header shown in Figure 14-6 on page 50 adds many benefits -- breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface -- and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 14-6; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 14-6 is common to all known emulators. The QACK signal shown in Figure 14-6 is usually connected to the PCI bridge chip in a system and is an input to the PC7410 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the PC7410 must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation, QACK should be merged via logic so that it also can be driven by the PCI bridge.
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Figure 14-6. COP Connector Diagram
From Target Board Sources (if any) SRESET HRESET QACK 13 11 HRESET SRESET 10 k 10 k 10 k 10 k 0 (5)
1 3 5 7 9 11 2 4 6 8 10 12
KEY
SRESET HRESET
(6)
OVDD OVDD OVDD OVDD
(6)
TRST 4 6 5(1) 15 Key 14(2) CHKSTP_IN
COP Header
TRST
VDD_SENSE 2 k CHKSTP_OUT 10 k 10 k 10 k
OVDD OVDD CHKSTP_OUT OVDD OVDD CHKSTP_IN
13 No pin 15 16
8 TMS 9 1 3 7 2 10 12 16 QACK NC NC 2 k(3) 10 k(4) TDO TDI TCK
TMS TDO TDI TCK QACK OVDD
COP Connector Physical Pin Out
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the PC7410. Connect pin 5 of the COP header to OVDD with a 10 k pull-up resistor. 2. Key location; pin 14 is not physically present on the COP header. 3. Component not populated. Populate only if debug tool does not drive QACK. 4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK. 5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect HRESET from the target source to TRST of the part through a 0 isolation resistor. 6. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully control the processor as shown above.
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Table 14-2.
Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
COP Pin Definitions
Connection TDO QACK TDI TRST No Connect VDD TCK CKSTP_IN TMS Optional. Add 10K pull-up to OVDD. Used on several emulator products. Useful for checkstopping the processor from a logic analyzer of other external trigger Add 2K pull-down to ground. Must be merged with on-board TRST if any See Figure 14-6 on page 50 Used on 604e; leave no-connect for all other processors Add 2K pull-up to OVDD (for short circuit limiting protection only) Add 2K pull-down to ground. Must be merged with on-board QACK, if any Special Notes
Signal TDO QACK TDI TRST RUN/STOP VDD_SENSE TCK CKSTP_IN TMS N/A SRESET N/A HRESET N/A CKSTP_OUT Ground
SRESET
Merge with on-board SRESET, if any
HRESET
Merge with on-board HRESET Key location; pin should be removed
CKSTP_OUT Digital Ground
Add 10K pull-up to OVDD
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the PC7410 are available on the Internet at www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the IEEE 1149.1 specification but is provided on all PowerPC implementations. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface is also used for accessing the common on-chip processor (COP) function of PowerPC processors, simply tying TRST to HRESET is not practical. The common on-chip processor (COP) function of PowerPC processors allows a remote computer system (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 14-6 on page 50 allows the COP to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The pull-down resistor on TRST ensures that the JTAG scan chain is initialized during power-on if a JTAG interface cable is not attached; if it is attached, it is responsible for driving TRST when needed.
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The COP header shown in Figure 14-6 on page 50 adds many benefits - breakpoints, watchpoints, register and memory examination/modification and other standard debugger features are possible through this interface - and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a "Berg" header). The connector typically has pin 14 removed as a connector key, as shown in Figure 14-6.
15. Ordering Information
xx
Product (1) Code
7410
Part Identifier
y
Temperature Range TJ (1)
xxx
Package (1)
y
Screening Level
nnnn
Max Internal (1) Processor Speed 400 MHz 450 MHz 500 MHz
L
Application (1) Modifier
x
Revision (1) Level
PC(X)
(2)
7410
V: -40C, +110C M: -55C, +125C
G: CBGA GS: CI-CBGA GH: HITCE
U: Upscreening blank: Std
L: 1.8V 100 mV N: 1.5V 50 mV
E
Notes:
1. For availability of the different versions, contact your local e2v sales office. 2. The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX partnumber is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes.
16. Definitions
16.1 Life Support Applications
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify e2v for any damages resulting from such improper use or sale.
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17. Document Revision History
Table 17-1 provides a revision history for this hardware specification. Table 17-1.
Rev. No F
Document Revision History
Date 01/07 Substantive Change(s) Name change from Atmel to e2v Table 8-1 on page 18: Changed note 1 to specify that OVDD and L2OVDD power is typically < 5% of VDD power Figure 12-5 on page 37: revised diagram and dimensions to specify `cap regions' versus individual cap measurements. Moved individual capacitor placement to separate figure Figure 12-6 on page 38: Added this figure to show each individual capacitor placement and value Figure 14-5 on page 47: updated COP Connector Diagram to recommend a weak pull-up resistor on TCK
E
10/2004
Table 9-1 on page 19: Changed measurement test condition IOH from -6mA to -5 mA for VOH and IOL from 6 mA to 5 mA for VOL per product bulletin "PLL and DLL Power Supply Filtering" on page 43: revised text regarding AVDD filter selection for the CBGA package Product specification release subsequent to product qualification Motorola changed to Freescale Figure 12-5 on page 37: added package capacitor values Section "Thermal Management Assistant": deleted Section "Pull-up Resistor Requirements" on page 47: added recommendation that strong pull-up/down resistors be used on the PLL_CFG[0:3] signals Table 9-3 on page 21: removed mode input setup and hold times. These inputs adhere to the general input setup and hold specifications
D
02/2004
Figure 9-4 on page 24: revised mode input diagram to show sample points around HRESET negation Figure 14-6 on page 50: added note 6 to emphasize that COP emulator and target board need to be able to drive HRESET and TRST independently to the CPU Section "PLL and DLL Power Supply Filtering" on page 43: revised section for HCTE package. Added text and figure for AVDD filter for the CBGA package Section "Pull-up Resistor Requirements" on page 47: removed AACK, TEA, and TS from control signals requiring pull-ups. Removed TBST from snooped transfer attribute list. TBST is an output and is not snooped
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Table of Contents
Features .................................................................................................... 1 Description ............................................................................................... 1 Screening ................................................................................................. 2 1 2 3 4 5 6 Block Diagram .......................................................................................... 3 General Parameters ................................................................................. 4 Overview ................................................................................................... 4 Signal Description ................................................................................... 8 Detailed Specification ............................................................................. 9 Applicable Documents ............................................................................ 9
6.1 Design and Construction ......................................................................................... 9 6.1.1 Terminal Connections ............................................................................. 9 6.2 Absolute Maximum Ratings ..................................................................................... 9 6.3 Recommended Operating Conditions ................................................................... 11
7
Thermal Characteristics ........................................................................ 12
7.1 Package Characteristics ........................................................................................ 12 7.1.1 Package Thermal Characteristics for HiTCE ......................................... 12 7.1.2 Package Thermal Characteristics for CI-CGA ....................................... 13 7.2 Internal Package Conduction Resistance ............................................................. 13 7.3 Thermal Management Information ........................................................................ 13 7.3.1 Adhesives and Thermal Interface Materials .......................................... 14
8
Power Consideration ............................................................................. 17
8.1 Power Management ..............................................................................................17 8.2 Power Dissipation .................................................................................................. 18
9
Electrical Characteristics ...................................................................... 19
9.1 Static Characteristics ............................................................................................. 19 9.2 Dynamic Characteristics ........................................................................................ 20 9.2.1 Clock AC Specifications ........................................................................ 20 9.2.2 Processor Bus AC Specifications .......................................................... 21 9.2.3 L2 Clock AC Specifications ................................................................... 24 9.2.4 L2 Bus AC Specifications ...................................................................... 26
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9.2.5 IEEE 1149.1 AC Timing Specifications ................................................. 28
10 Preparation for Delivery ........................................................................ 31
10.1 Handling .............................................................................................................. 31
11 Package Mechanical Data ..................................................................... 31
11.1 Parameters .......................................................................................................... 31
12 Pin Assignments .................................................................................... 32
12.1 BGA360 Package ................................................................................................ 32 12.2 Substrate Capacitors for the PC7410 .................................................................. 38 12.3 Substrate Capacitors for the PC7410 .................................................................. 40
13 Clock Selection ...................................................................................... 42 14 System Design Information .................................................................. 43
14.1 PLL and DLL Power Supply Filtering .................................................................. 43 14.2 Power Supply Voltage Sequency ........................................................................ 45 14.3 Decoupling Recommendations ........................................................................... 45 14.4 Connection Recommendations ........................................................................... 46 14.5 Output Buffer DC Impedance .............................................................................. 46 14.6 Pull-up Resistor Requirements ............................................................................ 47 14.7 JTAG Configuration Signals ................................................................................ 48
15 Ordering Information ............................................................................. 52 16 Definitions .............................................................................................. 52
16.1 Life Support Applications ..................................................................................... 52
17 Document Revision History .................................................................. 53 Table of Contents ...................................................................................... i
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How to reach us
Home page: www.e2v.com Asia Pacifiq Sales Office: United Kingdom e2v 106 Waterhouse Lane Chelmsford Essex CM1 2QU Tel: +44 (0)1245 493 493 Fax: +44 (0)1245 492 492 e2v Bank of China Tower 30th floor office 7 1 Garden Rd Central Hong Kong Tel: +852 2251 8227/8/9 Fax: +852 2251 8383
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